Higher circuit density and lower power-delay product have been the impetus for recent developments in bipolar technology. Exemplary features of today's advanced bipolar structures are self-aligned structure, deep-trench isolation and polysilicon emitter contact. Particularly, self-alignment techniques have significantly improved the performance of high speed bipolar transistors by reducing the extrinsic base-collector junction capacitance and the extrinsic base resistance. The most widely used self-alignment bipolar structure is the super self-aligned technology type (SST). See, for example, H. Nakashiba et al., IEEE Trans. Electron Devices., Vol. ED-27, No. 8, pp. 1390-94 (1980), T. H. Ning et al., IEEE Trans. Electron Devices., Vol. ED 28, No. 9, pp. 1010-13 (1981), and T. Sakai et al., Electron Letters, Vol. 19, No. 8, pp. 283-84 (1983).
The SST structure is generally characterized by overlapping double polysilicon layers. Typically, an underlying layer of polysilicon is used as a base electrode and an upper polysilicon layer is used as an emitter electrode. Moreover, with the underlying and upper polysilicon layers defining the extrinsic base and emitter regions, respectively, an oxide spacer or polysilicon spacer is introduced to separate the intrinsic and extrinsic transistor regions. The resulting transistor structure performs acceptably at high speed, but however, requires the intrinsic base region to be exposed to multiple etching after the formation of the base region. Such multiple etching results in an irregularity in the base region that is manifested as a non-uniformity in thickness along the lateral direction. More specifically, the irregular surface topography of the substrate is translated, upon diffusion therein with appropriate dopants, into a surface irregularity in the base region. Subsequent diffusion in forming the base-emitter interface creates a nonuniform dopant interface therebetween. Accordingly, the base region having a nonuniform dopant distribution at the emitter-base interface and an uniform dopant distribution at the base-collector interface produces a nonunformity in the base width along the lateral direction. Scaling the vertical doping profile and the horizontal dimensions so that all significant delay components are accordingly reduced is severely limited by this irregularity. For example, the nonunformity in base width makes it prohibitively difficult, if not impossible, to fabricate small and reproducible widths. Additionally, because the two polysilicon layers overlap, the surface topography is inherently non-planar, which could make subsequent fine line lithography steps difficult.
An alternative to the above self-alignment process has been proposed in which a first polysilicon layer is deposited to form the emitter region and a second polysilicon layer is subsequently deposited to form base contacts. More specifically, the first polysilicon layer, which is lightly implanted with emitter dopants, is deposited on a substrate having been previously implanted with base dopants. The second polysilicon layer is then deposited and subsequently heavily implanted with a base type dopant and heat treated for forming the emitter and extrinsic base regions. See, for example, A. Cuthbertson et al., IEEE Trans. Electron Devices, Vol., ED 32, No. 2 pp. 242-7 (1985), J. L. de Long et al. and Proc. of IEEE Bipolar Circuit and Technology Meeting, pp. 202-5 (1988). Advantageously, in the above process, the intrinsic region can be protected from the polysilicon over-etch process. However, in order to minimize the extrinsic base resistance and reduce the base-collector junction capacitance, several complicated process step are required. See, for example, T. Y. Chiu et al., IEDM 1988 Tech. Digest., pp. 752-5.
An important device parameter in high-speed bipolar devices is the base resistance, which consists of two components, the intrinsic base component and extrinsic base component. For all reported self-aligned bipolar structures, including the aforementioned structures above, it may be possible to utilize an digitated emitter geometry for minimizing the intrinsic base component. However, the necessity of contacting portions of the base region located between adjacent emitter fingers limits the spacing therebetween and, hence, the base-collector capacitance.
It is therefore an object of this invention to provide an improved self-aligned transistor having a lower base resistance, both intrinsic and extrinsic, for high speed applications. It is another object of this invention to provide an improved self-aligned transistor having a lower base-collector capacitance, especially for longer length emitter designs. It is still another object of this invention to provide an alternative method of fabricating self-aligned contacts in bipolar transistors without requiring the intrinsic base region to be exposed to multiple etching while minimizing the extrinsic base resistance. It is further an object of this invention to achieve surface planarity by eliminating the need for the emitter and base polysilicon layers to overlap. Finally, it is an object of the invention to reduce the processing complexity while using conventional material.